Advanced semiconductors: why the stack, not the node, sets the pace of AI

Public discussion of semiconductors centres on process nodes, as if the smallest transistor determined who leads. For a general-purpose processor that was largely true. For an AI accelerator it is not. The product is a package in which a logic die fabricated at a leading-edge node sits beside stacks of high-bandwidth memory (HBM) on a silicon interposer, all joined by advanced packaging that TSMC sells as CoWoS. A shortfall at any layer limits the number of finished accelerators regardless of how many logic wafers the foundry can print.

TSMC's own disclosures show where the pressure sits. High-performance computing accounted for 66 percent of its second-quarter 2026 revenue, and its full-year revenue growth guidance was raised to slightly above 40 percent in US dollars. Chief executive C.C. Wei told investors that the company's packaging capacity is so tight that it is now limiting his customers' growth, and that CoWoS remains the majority of its advanced packaging (Investing.com 2026b). The company that sets the pace of leading-edge logic says openly that the finishing step is the gating one.

The useful frame is a chain with four principal layers: lithography and equipment, leading-edge logic, memory, and packaging. Each has a different supplier structure, lead time, and policy exposure. Supply of the finished product equals the minimum of the four, and because they expand on different clocks, the binding layer moves over time. In 2026 the evidence says it is packaging and memory, not the node.

The shift follows from physics and economics. A single die is limited by the size of the lithographic field, roughly 800 square millimetres, and large dies lose yield rapidly as area grows. AI accelerators need more compute and far more memory bandwidth than one reticle-sized die can supply, so designers split logic into chiplets and place memory immediately beside them. The bandwidth wall, not arithmetic capacity, then limits performance, and that is why HBM and the interposer that carries it matter as much as the logic die.

Packaging is also harder to scale than it looks. Each package combines expensive dies, each of which must be tested before assembly because a single bad die wastes the others. The process uses substrates, interposers, and bonding equipment from a different supplier base than front-end wafer fabrication, and yields are learned on the line. TSMC's response has been to treat packaging as a capital programme: it allocates 10 to 20 percent of its 2026 capital budget to advanced packaging, testing, mask making, and other activities, is developing glass-substrate alternatives that Wei puts about a year from production readiness (Investing.com 2026b).

The consequence is a reversal of the old hierarchy. For decades, the foundry node was the scarce, strategic asset and packaging a commodity. For AI accelerators the economics have inverted: the node is available to anyone able to pay, while packaging slots and memory allocation are the rationed resources that decide who ships.

Concentration varies by layer but is high at each. In lithography, ASML is the sole supplier of extreme-ultraviolet (EUV) systems, with low-numerical-aperture capacity of around 65 systems in 2026 and plans to add 30 percent in 2027, and on 15 July 2026 it reported that Intel Foundry is using its High-NA EUV systems in volume production of part of its Core Ultra Series 3 processors on the 18A node (ASML 2026a; ASML 2026b). For logic, TrendForce estimates Taiwan holds about 68 percent of global capacity at 16/14 nanometres and below, and 80 percent of EUV-enabled capacity, falling toward 60 percent by 2027 as other regions add capacity (Bits & Chips n.d.).

Memory is split among three firms but the shares move quickly. Counterpoint Research's second-quarter 2026 data put SK hynix at 50 percent of HBM revenue, Samsung at 33 percent, up from 21 percent in the first quarter, and Micron at 18 percent. Samsung's gain came from HBM4, which it began shipping in volume in February for Nvidia's Vera Rubin platform, while SK hynix defended its position with HBM3E (Seoul Economic Daily 2026). Packaging is the most concentrated of all, since TSMC dominates CoWoS and says it is not yet able to meet demand.

The suppliers' guidance shows how much demand is pressing on the narrowest layers. TSMC raised its 2026 capital budget to 60 to 64 billion dollars from 52 to 56 billion, allocating 70 to 80 percent to advanced process technologies, and said spending over the next three years will be significantly higher than over the past three. It also announced an additional 100 billion dollars of Arizona investment for two-nanometre-and-below fabs and advanced packaging, with no firm timing given for the packaging plants (Investing.com 2026b). ASML raised its 2026 net sales guidance to 43 to 45 billion euros and said order intake remained extremely strong in the first half (ASML 2026a).

The memory squeeze is the clearest sign that the constraint is shared across layers. HBM consumes the same DRAM wafer capacity as conventional memory, so diverting capacity to HBM tightens supply of ordinary server and consumer DRAM. Counterpoint notes that most HBM revenue still comes from HBM3E and that HBM4 only becomes meaningful in the second half of 2026, so the memory layer is mid-transition just as demand peaks (Seoul Economic Daily 2026). Expansion is limited by cleanroom space and by the specialised bonding and etching tools needed for stacking. A packaging expansion that is not matched by memory leaves accelerators without their memory; a memory expansion without packaging leaves memory without a package.

Efficiency of expansion differs by layer. Foundry capacity can be added in two to three years at high cost. EUV tool output is limited by ASML's own supply chain. Packaging capacity can be expanded faster than fabs but still requires qualification with each customer. These unequal clocks explain why shortages recur even as total spending rises.

Export controls have been aimed mainly at two layers, lithography and finished chips. ASML has never shipped an EUV system to China, a restriction in place since 2019, and Dutch licences also cover the most advanced immersion DUV systems and servicing of some installed tools. A bill introduced in the US House in April 2026, the MATCH Act, would extend restrictions to older equipment and to servicing of machines already delivered, and Dutch officials were reported in August to be lobbying to remove it (NL Times 2026). ASML says China will remain about 20 percent of its 2026 sales, down from a much higher share in 2025, with additional demand primarily in logic serving domestic customers (Investing.com 2026a).

The chip rules have been less stable. On 15 January 2026, the Bureau of Industry and Security moved review of exports of Nvidia's H200 and AMD's MI325X to China from presumption of denial to case-by-case, conditional on showing that exports will not reduce capacity available to US customers, that the buyer has export-compliance procedures, and that the products have been independently tested in the United States (Bureau of Industry and Security 2026). Nvidia received a licence for a small amount of H200 exports in February, subject to a 25 percent duty, and later reports described shipments as very few (Bloomberg 2026). Congressional proposals such as the AI OVERWATCH Act would ban Blackwell-class sales to China for at least two years. Policy has oscillated between tightening and licensing within a single year.

China's response has been to attack the layers the controls do not reach. Analysts report that Huawei's Ascend output depends increasingly on SMIC wafers and domestic packaging, that the stock of dies made earlier at TSMC is effectively exhausted, and that HBM is the binding constraint on volume (SemiAnalysis 2025). CXMT has reportedly begun small-scale HBM3E production while its HBM3 mass-production timeline has slipped (Digitimes 2026). Whether SMIC's most advanced node is truly five-nanometre class remains contested. The lesson is that controls on tools and chips raise costs and slow China at the frontier, but a determined actor routes around them through volume, packaging, and memory.

Diversification is under way but incomplete. TSMC's first Arizona fab produces chips at four nanometres for Nvidia's Blackwell family, the company has committed a further 100 billion dollars to the site, and about four more fabs including packaging are planned, though management says timing will depend on market conditions (Investing.com 2026b). Intel entered risk production of its 18A-P process in June 2026 and expects foundry customer commitments in the second half of the year, with the US government holding a 10 percent equity stake since August 2025 (CNBC 2026).

Packaging is the missing piece. TSMC has reportedly told Reuters that its first advanced packaging facility in Arizona is targeted for 2029, later than earlier Taiwanese press reports of the end of 2027 (Tech Insider 2026). Until then, wafers made in Arizona must travel to Taiwan to be packaged, which means the geopolitical concentration the fab was meant to reduce persists in the last step of the chain. A leading-edge chip fabricated in the United States is not yet a chip the United States can finish.

The cost and execution risks are real. Taiwanese officials have reportedly named water supply, regulation, visa delays, and labour as constraints on the Arizona build, and chips made there are expected to cost materially more (Tech Insider 2026). Diversification will therefore advance layer by layer, starting where capital and skills transfer easily, and lag where tacit know-how and supplier clusters, as in packaging, remain in Taiwan.

The strongest objection is that the bottleneck is temporary. TSMC is working to narrow a supply gap that Wei called very big, Intel and others offer alternative packaging, and glass substrates are about a year from production readiness (Investing.com 2026b). Custom accelerators from hyperscalers diversify demand away from a single customer. Demand itself could soften if AI revenue disappoints,. Each of these narrows the thesis without removing it: the binding layer moves, and the question is where it moves to.

Three paths follow. In packaging catch-up, expansion at TSMC and its partners relieves the gate by 2028, and memory and equipment become the binding layers, so HBM4 yield and EUV output set the pace. In a split stack, China builds a domestic chain around SMIC, Huawei, and CXMT that is smaller and costlier but outside Western controls, and the world divides into two compute supply systems. In relocation, Arizona and Intel Foundry reach full-stack capability including packaging, which lowers the Taiwan concentration but at higher cost. Signposts include the timing of Arizona's packaging plant, the HBM share trajectory between SK hynix and Samsung, the outcome of the MATCH Act, Chinese HBM output, and TSMC's disclosure of whether packaging still limits customers.

The comparative evidence supports a selective conclusion. Access to frontier AI compute goes to buyers who secure allocation across the stack, not just chips: wafer commitments, HBM supply, and packaging slots, usually through multi-year prepayments that only the largest firms can make. It stalls for those who treat the accelerator as a catalogue item. Countries and firms that can pair leading-edge logic with memory and packaging, or ally with those who do, will compound their lead; those that control one layer but depend on others will find their leverage conditional.

For governments, the implication is that a policy aimed at a single layer is easily bypassed, and industrial strategy has to cover the middle of the chain, especially packaging and memory, where capacity is both scarce and slow to relocate. For firms, supply planning should map exposure by layer and by supplier concentration, and treat packaging and HBM allocation as strategic procurement. For investors, the scarcest layer earns the margin: the winners are those who hold packaging and memory capacity or tools, not those who assume that node leadership alone decides the outcome.

The silicon in an AI accelerator is only part of the product. The pace of AI is set by the slowest, most concentrated layer between the wafer and the finished package, and for the next several years that layer is no longer the transistor.